Method and apparatus for iterative timing and carrier recovery

ABSTRACT

Method and apparatus for iterative timing recovery for FTN signaling are provided. The iterative timing recovery method and apparatus uses a feedback timing error signal from a forward error correction block with an additional equalizer prior to a maximum a posteriori (MAP) decoder which matches the equalized FTN signal to a truncated inter-symbol interference (ISI) target. A timing error is then generated using a modified M&amp;M timing error detector.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 61/217,333, entitled “SYSTEM AND METHODS FOR SATELLITE SYSTEMS,”filed May 29, 2009 which is incorporated by reference herein in itsentirety.

FIELD OF THE INVENTION

The present principles relate to iterative timing recovery in receiverssystems.

BACKGROUND OF THE INVENTION

Carrier recovery schemes can be classified into two structures:feed-forward structure and feedback structure.

The feedback carrier recovery uses a digital Phase Locked Loop (PLL) totrack out the carrier phase and frequency offset. However, it relies ona decision directed or non-data-aided approach to estimate the phaseerror at each time instant. In decision-directed approach, the decisionerrors will cause additional self noise while the non-data-aidedapproach can only apply to a limited number of multiple phase shiftkeying (MPSK) formats. Further, the feedback carrier recovery schemecould be disturbed by cycle slips which may cause a large number oferrors due to phase ambiguity. Feed forward carrier recovery is used toreduce the probability of cycle slips.

The feed forward carrier recovery relies on pre-known data symbols (e.g.pilot or sync symbols) embedded in the data stream. This reduces thebandwidth efficiency since no data is transmitted during a pilot or syncinterval. The second disadvantage of the feed-forward carrier recoveryis the inability to recover large frequency offsets or phase variationsdue to phase noise between the measurement blocks.

Faster-than-Nyquist (FTN) signaling has become important for the nextgeneration of transmission systems since FTN allows an easy trade-offbetween Signal-to-Noise Ratio (SNR), bandwidth (BW) and bit error rate(BER). Timing recovery in FTN signaling becomes a huge challenge due tostrong ISI effects when the symbols period is squeezed to get higherbandwidth efficiency.

Under the principles of the present invention, an iterative timingrecovery is suggested for FTN signaling using a feedback timing errorsignal from the forward error correction (FEC) block. The FEC blockcould be realized by a so-called soft decoder like Low Density ParityCheck (LDPC), a turbo decoder or a soft output Viterbi algorithm (SOVA).In the current idea a MAP decoder is used to match the intersymbolinterference (ISI) response of the FTN signal. An additional equalizeris utilized in front of the maximum a posteriori (MAP) decoder whichmatches the equalized FTN signal to the truncated ISI target. The timingerror is then generated by using a modified Mueller and Muller (M&M)timing error detector (TED).

The iterative symbol timing recovery is used when ISI becomes a severeproblem for FTN signaling.

SUMMARY OF THE INVENTION

These and other drawbacks and disadvantages of the prior art areaddressed by the present principles, which are directed to a method andapparatus for iterative timing and carrier recovery in phase shiftkeying systems.

According to an aspect of the present principles, there is provided amethod for iterative timing recovery. The method comprises performingadaptive equalization and maximum likelihood sequence estimation inorder to recover symbol timing.

According to another aspect of the present principles, there is alsoprovided an apparatus for iterative timing recovery comprising ancomprising adaptive equalizer for performing adaptive equalization and asymbol detector for performing maximum likelihood sequence estimation inorder to recover symbol timing.

According to another aspect of the present principles, there is alsoprovided a method for iterative timing recovery comprising filtering aninterpolated first error signal using a matched filter, equalizing thefiltered interpolated first error signal, detecting a timing error withan M&M timing error detector to produce a second error signal, and usingsaid second error signal to recover the timing of a signal that usesfaster-than-Nyquist signaling.

According to another aspect of the present principles, there is alsoprovided an apparatus for iterative timing recovery. The apparatuscomprises a matched filter for filtering an interpolated first errorsignal using a matched filter, an equalizer for equalizing the filteredinterpolated first error signal, a timing error detector for detecting atiming error with an M&M timing error detector to produce a second errorsignal, and a recovery circuit for using said second error signal torecover the timing of a signal that uses faster-than-Nyquist signaling.

These and other aspects, features and advantages of the presentprinciples will become apparent from the following detailed descriptionof exemplary embodiments, which is to be read in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an apparatus for least-mean-square error (LMSE) estimationwith equalization for FTN signaling.

FIG. 2 shows an apparatus for iterative timing recovery for FTNsignaling.

FIG. 3 shows a method for iterative timing recovery.

FIG. 4 shows a method for iterative timing recovery for FTN signaling.

DETAILED DESCRIPTION

An approach for iterative time recovery for transmission systems isdescribed herein.

FTN signaling can be modeled as a channel response with memory.Furthermore, the optimum signal detector in an Additive White Gaussiannoise (AWGN) band limited channel is the maximum likelihood detector ormaximum a posteriori detector if a priori information is available. Itis also clear that the optimum symbol detector for FTN signaling reliesnot only on the current symbol but also the neighbor symbols. Theinterference introduced by the neighbor symbols is called inter-symbolinterference (ISI). The ISI distorted signals are modeled with a trellisstructure and its memory is often infinite. So infinite states in thetrellis have to be considered for symbol detection. One way to solvethis problem is to reduce the number of states in the decoding processby using sub-optimum decoding structures. In this disclosure, the ideaof Maximum Likelihood Sequence Estimation (MLSE) is used to achieve theoptimum detection performance for channels with memory. Neverthelessmodifications have to be done on the MLSE by the reduction of the numberof states which is realized by the truncation of the ISI response andleads to a suboptimum but realizable symbol detection. It is clear thatthe truncation skews the frequency response of the ISI distorted signaland so the MLSE is modified to a combination of MLSE and adaptiveequalization detection, which is further described herein.

The Maximum Likelihood Sequence Estimation (MLSE) was first mentioned byForney and Viterbi [Fo73] and an optimum detection was given by Viterbi[Vit67] with the Viterbi decoder, which estimates the maximum likelihoodpath (maximum likelihood sequence) through the trellis. Bahl, Cocke,Raviv and Jelinek further improve the maximum likelihood sequenceestimation by the BCJR algorithm [BCJR74] which generates soft outputvalues for each symbol decision. In this thesis a BCJR algorithm isdescribed for FTN signal detection whereas the complexity is furtherreduced by a Max-log-MAP decoder [Ko90] [Er94]. The Max-log-MAP decoderrelies on a backward and forward recursion through the trellis. The mostimportant step on the design of a Maximum Likelihood Sequence Estimation(MLSE) decoder is the definition of the state transition probabilitiesor so-called branch metrics. Therefore the Euclidian distance betweenthe received symbol y and the ISI response targets t(s,s′) is evaluatedas it is shown in equation

X(s,s′)=∥y[nT _(s) ]−t(s,s′)ν²  (1)

Where s denotes the successor states and s′ denotes the current state inthe trellis. The targets t(s,s′) for each state transition are generatedby folding the possible candidates in the channel memory with thetruncated ISI response waveform hm with the truncated ISI length L. Fora BPSK modulation we get

$\begin{matrix}{{t\left( {s,s^{\prime}} \right)} = {\sum\limits_{k = 0}^{L}{a_{m}h_{m - k}}}} & (2)\end{matrix}$

The Max-log-MAP decoding process is then further divided into theforward, backward recursions and the a posteriori log likelihood ratiosLLR computation [WH00]. An example for BSPK modulation is provided asfollowing:

$\begin{matrix}{\mspace{79mu} {{(1)\mspace{14mu} {Forward}\mspace{14mu} {recursion}}\mspace{121mu} {{A_{k}(s)} = {\max\limits_{s^{\prime}}\left( {{A_{k - 1}\left( s^{\prime} \right)} + {x_{k}\left( {s^{\prime},s} \right)}} \right)}}}} & (3) \\{\mspace{79mu} {{(2)\mspace{14mu} {Backward}\mspace{14mu} {recursion}}\mspace{121mu} {{B_{k}\left( s^{\prime} \right)} = {\max\limits_{s}\left( {{B_{k - 1}(s)} + {x_{k}\left( {s^{\prime},s} \right)}} \right)}}}} & (4) \\{{(3)\mspace{14mu} A\mspace{14mu} {posteriori}\mspace{14mu} L\; L\; R\mspace{14mu} {computation}}\mspace{40mu} {{L\left( {u_{k}y_{k}} \right)} = {{\max\limits_{u_{k} = 1}\left( {{A_{k - 1}\left( s^{\prime} \right)} + {B_{k}(s)} + {x_{k}\left( {s^{\prime},s} \right)}} \right)} - {\max\limits_{u_{k} = 0}\left( {{A_{k - 1}\left( s^{\prime} \right)} + {B_{k}(s)} + {x_{k}\left( {s^{\prime},s} \right)}} \right)}}}} & (5)\end{matrix}$

Note that the subscript k denotes the time index of the trellis.

We mention that the truncated ISI response has to be used to implement arealizable MLSE detector. Note that there is still an amplitudedifference between the truncated ISI response H_(ISI)(j) and the trueISI response H_(post)(j). Therefore an adaptive equalizer should be usedbefore the MLSE detector. To adapt the equalizer the least-mean-squareerror (LMSE) adaptation [Hay01] is used. The LMSE adaptation minimizesthe least mean square error between the equalized symbol y′(nT_(s)) andthe desired symbol d(nT_(s)) given in following equation.

e(nT _(s))=y(nT _(s))−d(nT _(s))  (6)

The LMSE with equalization is shown in FIG. 1. The filter coefficientvector w(nT_(s)) can be expressed as following:

w(nT _(s))=w((n−1)T _(s))+μ[e(nT _(s))×(nT _(s))],  (7)

where x(nT_(s))=[y(nT_(s)), y((n−1)T_(s)), . . . , y((n−L+1)T_(s))]^(T),L the length of the FIR filter and (□)^(T) represent the transposeoperation and μ is the step size.

The performance of the classical timing error detection degrades whenFTN signaling is used. A modified symbol detector based on MLSEequalization is mentioned above. To improve the timing error detectorperformance of the fine step in the two-step approach proposed inanother disclosure by the applicant, an MLSE equalization iterativetiming error detector is proposed in this disclosure. To implement theiterative timing recovery the equation for the iterative searchprocessing for the timing error ε′(nT_(s)) based on steepest descentgiven in [MMF98] is adapted to our system.

$\begin{matrix}{{ɛ^{\prime}\left( {\left( {n + 1} \right)T} \right)}_{s} = {{ɛ^{\prime}\left( {nT}_{s} \right)} + {\alpha \frac{\partial}{\partial ɛ^{\prime}}{L\left( {{{y\left( {nT}_{s} \right)}a},ɛ^{\prime}} \right)}}}} & (8)\end{matrix}$

To maximize the objective function L(y(nT_(s))|a, ε′) regarding thetiming error ε′ we use a modified M&M timing error detector to considerthe ISI distortion in the timing error estimation. The modified M&Mtiming error detector is then given as

ε′(nT _(s))=Re[(a″(nT _(s)))*y′(nT _(s) −T _(s)+ε)−(a″(nT _(s) −T_(s)))*y′(nT _(s)+ε)],  (9)

where y′(nT_(s)) is the equalizer output, a′(nT_(s)) denotes the currentdecision from the MAX-LOG-MAP decoder and a′(nT_(s)) is convolved withtruncated impulse response to produce a″(nT_(s)) using Equation (2). Theproposed iterative timing recovery for FTN signaling is shown in FIG. 2.

One embodiment of the present principles is illustrated in FIG. 1, whichshows an apparatus for iterative timing recovery. An FIR filter is usedto filter an input signal. The input signal is also in signalcommunication with a first Max-log-Map and Equalizer block. The FIRfilter has coefficients under control by a Least Mean Squared (LMS)block. The LMS block takes as input the output of the first Max-log-Mapand Equalizer block, and the output of a summing circuit. The summingcircuit has a non-inverting input that is in signal communication with asecond Max-log-Map circuit, and a second inverting input coming from atarget pulse shaping circuit. The FIR filter output is in signalcommunication with the second Max-log-Map circuit and a thirdMax-log-Map circuit. The output of the third Max-log-Map circuit is insignal communication with the input of the target pulse shaping blockand is used as an output of the apparatus. The output of the secondMax-log-Map circuit is also an output of the apparatus that isrepresentative of the equalized symbol.

Another embodiment of the present principles is illustrated in FIG. 2,which shows an apparatus for iterative timing recovery forfaster-than-Nyquist (FTN) signaling. An interpolator output is in signalcommunication with the input of a matched filter, whose output is insignal communication with an equalizer. The equalizer output is insignal communication with a Max-log-Map block, and in signalcommunication with a first input of an Mueller & Muller (M&M) timingerror detector (TED) block. The Max-log-Map block's output is in signalcommunication with the input of an inter-symbol interference (ISI)filter, whose output is in signal communication with a second input ofthe M&M TED. The M&M TED's output is in signal communication with afirst input of a multiplier circuit, whose second input is a variable.The output of the multiplier circuit is in signal communication with afirst non-inverting input of a summing circuit, whose second input is adelayed version of the summing circuit output, which is also in signalcommunication with the interpolator input.

Another embodiment of the present principles is illustrated by FIG. 3,which shows a method for interative timing recovery. The method iscomprised of an adaptive equalization step 310 and a Mean Least Squaredestimation step 320.

Another embodiment of the present principles is illustrated by FIG. 4,which shows a method for itnerative timing recovery for FTN signaling,comprising the steps of filtering 410, equalizing 420, detecting 430 andrecovering timing 440.

The functions of the various elements shown in the figures may beprovided through the use of dedicated hardware as well as hardwarecapable of executing software in association with appropriate software.When provided by a processor, the functions may be provided by a singlededicated processor, by a single shared processor, or by a plurality ofindividual processors, some of which may be shared. Moreover, explicituse of the term “processor” or “controller” should not be construed torefer exclusively to hardware capable of executing software, and mayimplicitly include, without limitation, digital signal processor (“DSP”)hardware, read-only memory (“ROM”) for storing software, random accessmemory (“RAM”), and non-volatile storage.

Other hardware, conventional and/or custom, may also be included.Similarly, any switches shown in the figures are conceptual only. Theirfunction may be carried out through the operation of program logic,through dedicated logic, through the interaction of program control anddedicated logic, or even manually, the particular technique beingselectable by the implementer as more specifically understood from thecontext.

A description will now be given of the many attendant advantages andfeatures of the present principles, some of which have been mentionedabove. For example, one advantage is a method for iterative timingrecovery comprising performing adaptive equalization and maximumlikelihood sequence estimation in order to recover symbol timing.Another advantage is an apparatus for iterative timing recoverycomprising an comprising adaptive equalizer for performing adaptiveequalization and a symbol detector for performing maximum likelihoodsequence estimation in order to recover symbol timing. Another advantageis a method for iterative timing recovery comprising filtering aninterpolated first error signal using a matched filter, equalizing thefiltered interpolated first error signal, detecting a timing error withan M&M timing error detector to produce a second error signal, and usingsaid second error signal to recover the timing of a signal that usesfaster-than-Nyquist signaling. Yet another advantage is an apparatus foriterative timing recovery comprising a matched filter for filtering aninterpolated first error signal using a matched filter, an equalizer forequalizing the filtered interpolated first error signal, a timing errordetector for detecting a timing error with an M&M timing error detectorto produce a second error signal, and a recovery circuit for using saidsecond error signal to recover the timing of a signal that usesfaster-than-Nyquist signaling.

The present description illustrates the present principles. It will thusbe appreciated that those skilled in the art will be able to devisevarious arrangements that, although not explicitly described or shownherein, embody the present principles and are included within its spiritand scope.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the presentprinciples and the concepts contributed by the inventor(s) to furtheringthe art, and are to be construed as being without limitation to suchspecifically recited examples and conditions.

Moreover, all statements herein reciting principles, aspects, andembodiments of the present principles, as well as specific examplesthereof, are intended to encompass both structural and functionalequivalents thereof. Additionally, it is intended that such equivalentsinclude both currently known equivalents as well as equivalentsdeveloped in the future, i.e., any elements developed that perform thesame function, regardless of structure.

Thus, for example, it will be appreciated by those skilled in the artthat the block diagrams presented herein represent conceptual views ofillustrative circuitry embodying the present principles. Similarly, itwill be appreciated that any flow charts, flow diagrams, statetransition diagrams, pseudocode, and the like represent variousprocesses which may be substantially represented in computer readablemedia and so executed by a computer or processor, whether or not suchcomputer or processor is explicitly shown.

In the claims hereof, any element expressed as a means for performing aspecified function is intended to encompass any way of performing thatfunction including, for example, a) a combination of circuit elementsthat performs that function or b) software in any form, including,therefore, firmware, microcode or the like, combined with appropriatecircuitry for executing that software to perform the function. Thepresent principles as defined by such claims reside in the fact that thefunctionalities provided by the various recited means are combined andbrought together in the manner which the claims call for. It is thusregarded that any means that can provide those functionalities areequivalent to those shown herein.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

1. A method for iterative timing recovery, comprising: performingadaptive equalization on an input signal; performing maximum likelihoodsequence estimation on the adaptively equalized input signal to detectsymbol timing.
 2. An apparatus for symbol timing recovery, comprising:an adaptive equalizer for performing adaptive equalization on an inputsignal; a symbol detector for performing maximum likelihood sequenceestimation on the adaptively equalized input signal to detect symboltiming.
 3. A method for iterative timing recovery, comprising: filteringan interpolated first error signal using a matched filter; equalizingthe filtered interpolated first error signal; detecting a timing errorwith an M&M timing error detector to produce a second error signal.using said second error signal to recover the timing of a signal thatuses faster-than-Nyquist signaling.
 4. An apparatus for iterative timingrecovery, comprising: a matched filter for filtering an interpolatedfirst error signal using; an equalizer for equalizing the filteredinterpolated first error signal; a timing error detector for detecting atiming error with an M&M timing error detector to produce a second errorsignal. a recovery circuit for recovering the timing of a signal thatuses faster-than-Nyquist signaling using said second error signal.